Cross-office connecting scheme for interconnecting multiplexers and central office terminals

ABSTRACT

Interchange of data between two way loops and a data trunk is provided by way of channel units, submultiplexer/demultiplexers and a common multiplexer/demultiplexer. Submultiplexers have five, 10 or 20 ports, creating time frames with corresponding numbers of time slots, all of equal duration. The channel units, which terminate 9.6, 4.8 or 2.4 Kbs data subscribers, assemble the incoming data into bytes, repeat each byte five, 10 or 20 times, respectively, and align each successive one of the repeated bytes with successive time slots. Any port of a five port submultiplexer can be connected to any 9.6, 4.8 or 2.4 channel unit. Similarly, any port of a ten port submultiplexer can be connected to any 4.8 or 2.4 channel unit and any port of a twenty port submultiplexer can be connected to any 2.4 channel unit. The outputs of all submultiplexers are interleaved by the common multiplexer and applied to the trunk. Incoming data from the trunk is distributed to the several submultiplexers/demultiplexers which, in turn, distribute the data to the channel units.

FIELD OF THE INVENTION

This invention relates to a time-division multiplex system and moreparticularly, to a system wherein data signals derived from a datachannel are interleaved with the signals from other data channels.

DESCRIPTION OF THE PRIOR ART

When a plurality of data channels or lines are handled by a commonfacility, it is generally convenient to multiplex the signals from theseveral lines on a common path or bus. Each incoming line is connectedto an input port of the multiplex system. The input ports aresequentially scanned; during each scan cycle or frame a time slot isallocated to each input port; and a data signal from each incoming lineis applied to the common bus during the interval defined by the timeslot. The multiplex signals on the bus are then transmitted to a remotefacility where they are demultiplexed and distributed to variousoutgoing lines corresponding to the incoming lines at the localfacility. Alternatively, if the facility is handling a large number oflines, the input ports are arranged into groups and each group of portsis scanned by a submultiplexer. The signals on the varioussubmultiplexer busses are then interleaved by a common officemultiplexer.

In the large facilities, the data subscribers have many and differingrequirements. Certain of the signaling lines may be dedicated to adifferent code format and different signaling rates. Varioushousekeeping and supervisory signals may have to be transmitted.Advantageously, in the large facility, incoming signaling bits areassembled with locally generated supervisory and housekeeping bits intodata bytes. In addition to inserting supervisory and housekeepinginformation into each byte, the effect of the bit stuffing is to createa byte repetition rate that is the same as the time frame repetitionrate of the submultiplexer so that one byte from each port is insertedonto the busses in each time frame, the bits of each byte being seriallyapplied to the bus during the time slot allocated to the input port.

Data subscribers in the large facility desire to be rerouted from timeto time; connections to ports are severed and new subscribers connectedthereto. Since the data byte assembler differs in operation with thedifference in requirements from subscriber to subscriber, it ispreferable that the assembler is assigned to the input line circuit andterminal of each subscriber rather than to the submultiplexer inputport. To provide office flexibility, however, the assembler must beprepared to present the byte during any one of the time slots (asdetermined by the input port connected thereto). Moreover, since largephysical distances usually separate line circuits and terminals from theoffice submultiplexers, serial signaling is preferable to minimize thenumber of wires in the terminal-to-port cross-connection.

Accordingly, it is an object of this invention to provide flexibility inmultiplex systems of the above-described type.

It was previously indicated that bit stuffing permits subscribers ofdiffering signaling rates to be accommodated by the same multiplexer;the lower the signaling rate of the subscriber, the greater the numberof stuffed bits and the fewer the number of data bits in the byte. Ifthe signaling rate of some subscribers are much lower, one-half orone-fourth the signaling rate of the higher rate subscribers, forexample, the corresponding large number of stuffed bits results inwasted transmission time. It is preferable, therefore, that these lowrate subscribers be grouped together and assigned a separatesubmultiplexer. If such subscribers are limited to this "low rate"submultiplexer, however, the office cross-connection flexibility isreduced.

It is therefore another object of this invention to permit low ratesubscribers the option of connecting to any submultiplexer.

SUMMARY OF THE INVENTION

In general, line terminals providing bytes having a repetition ratewhich is the same as the time frame repetition rate of thesubmultiplexer, repeat each byte a plurality of times equal in number tothe number of time-frame time-slots (or the number of submultiplexerinput ports) and align each successive one of the repeated bytes witheach successive one of the time slots. The submultiplexer, in scanningthe repeated bytes applied to each of the input ports, passes to thebusses the one repeated byte that is aligned with the time slotallocated to the input port. The terminal can therefore optionally beconnected to any port and office cross-connect flexibility is preserved.

Line terminals which provide a byte repetition rate which is one-halfthe rate of the aforementioned "higher-rate" terminals can connect to a"half-rate" submultiplexer or to the above-described "higher-rate"submultiplexer. The "half-rate" submultiplexer has twice the number ofinput ports (and time slots/frame) as the "full-rate" submultiplexer andthe "half-rate" terminal repeats each byte the same number of times asthe number of time slots in the "half-rate" time frame (or twice thenumber of times as the "higher-rate" terminals), aligning successivebytes with successive time slots. This permits any "half-rate"subscriber to be connected to any port of the "half-rate"submultiplexer. The time slots of the "half-rate" submultiplexer,however, have the same duration and are aligned in time with the timeslots of the "higher-rate" submultiplexer, whereby all submultiplexersscan the input ports at the same rate. Therefore, the "half-rate"subscriber can connect to any port of the "higher-rate" submultiplexer,although, since the data byte is repeated twice as many times, therepeated byte appears in each of two successive scans or frames.

In a similar manner, subscribers having a one-fourth signaling rate canconnect to a submultiplexer having four times as many ports. Optionally,they can be connected to any port of a "half-rate" or a "higher-rate"submultiplexer.

It is an advantage of this invention that all of the various ratesubmultiplexers have the same scanning rate and thus equal duration timeslots. This enables a conventional office multiplexer to interleave theoutput data of the several submultiplexers.

The foregoing and other objects and features of this invention will bemore fully understood from the following description of an illustrativeembodiment taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawing:

FIG. 1 discloses, in block form, a central office facility arranged inaccordance with this invention;

FIG. 2 shows, in schematic form, the various circuits which form asubmultiplexer/demultiplexer in accordance with this invention;

FIG. 3 shows, in schematic form, the various circuits which form a lineterminal (hereinafter called an office channel unit) and the variouscircuits which form a local clock circuit common to a group of officechannel units, in accordance with this invention; and

FIG. 5 comprised of FIGS. 4A and 4B depict the various waveforms of theoffice clock signals and the data signal outputs of thesubmultiplexer/demultiplexers and office channel units.

DETAILED DESCRIPTION

In accordance with a specific arrangement of applicants' invention, atwo-way trunk, such as trunk 101 shown in FIG. 1, interchanges data witha plurality of two-way loops, typical ones of the loops being identifiedas loops 102 through 105. In accordance with one specific arrangement, aset of loops, including two-way loop 102 and other loops not shown,extends to data customers or subscribers who send and receive data at a64 kilobit per second (Kbs) signaling rate (or, optionally, a 56 Kbsrate); a set of loops, including two-way loops 103, extends to datasubscribers having a 9.6 Kbs signaling rate; and two sets of loops,including two-way loops 104 and 105, are connected to 4.8 Kbs and 2.4Kbs data customers, respectively.

The interchange of data between the two-way subscriber loops and trunk101 is provided by a plurality of office channel units, typical ones ofthe units being identified by blocks 106 through 113; groups ofsubmultiplexer/demultiplexers, typical ones being identified by blocks116 through 118; and multiplexer/demultiplexer 115. Each of two-wayloops 102 through 105 terminates in one of office channel units 106through 113. Digital data from each subscriber is processed through theassociated office channel unit, in a manner described in detailhereinafter, and applied to an office channel unit terminal and,conversely, data obtained from each channel unit terminal is processedthrough the channel unit and applied to the subscriber loop. Typicalones of the terminals are identified in FIG. 1 as terminals 119 through125.

Terminals 119 through 125 are arranged to be optionally strapped tovarious cross-office path terminals, such as terminals 126 through 136.Terminals 126 through 136 are, in turn, connected to two-waycross-office paths 137 through 143. In FIG. 1, office channel unitterminal 119 is shown strapped to cross-office path terminal 136,thereby interconnecting office channel unit 106 with two-waycross-office path 143. Similarly, terminal 120 is shown strapped toterminal 135 to interconnect office channel unit 107 to two-way path142. Other strappings to connect terminals are also shown in FIG. 1.

Returning now to two-way cross-office path 143, this path is connectedto multiplexer/demultiplexer 115, and more specifically, to a portidentified as port 1. Multiplexer/demultiplexer 115 includes 23 portsand, as described hereinafter, data applied to the several ports ismultiplexed and the multiplexed data is transmitted to trunk 101 andincoming multiplexed data on trunk 101 is demultiplexed and distributedto the several ports.

As seen in FIG. 1, two-way paths 137 through 142 are connected to portsof submultiplexer/demultiplexers 116 through 118.Submultiplexer/demultiplexer 116 includes five ports, port 1 beingconnected to path 142 and the other ports being connected to the otherones of the cross-office paths. The common two-way trunk path 144 ofsubmultiplexer/demultiplexer 116 is connected to an intermediate port ofmultiplexer/demultiplexer 115. The office may include one or more otherfive-port submultiplexer/demultiplexers, each having their commontwo-way trunk path connected to individual ports ofmultiplexer/demultiplexer 115 and having their ports connected totwo-way cross-office paths. The office also includes 10-portsubmultiplexer/demultiplexers, such as submultiplexer/demultiplexer 117,and 20-port submultiplexer/demultiplexers, such assubmultiplexer/demultiplexer 118. The common two-way trunk ofsubmultiplexer/demultiplexer 117 is connected by way of two-way path 145to a port of multiplexer/demultiplexer 115 and the common trunk path ofsubmultiplexer/demultiplexer 118 is connected by way of two-way path 146to another port of multiplexer/demultiplexer 115, in this case beingidentified as port 23.

In accordance with the general organization of the office, each of the64 Kbs subscribers interchanges data with a port ofmultiplexer/demultiplexer 115 by way of an office channel unit and eachof the subscribers having other signaling rates interchanges data withports of multiplexer/demultiplexer 115 by way of asubmultiplexer/demultiplexer. Advantageously, each of the 9.6 Kbs officechannel units, such as office channel unit 107, is optionally connectedto one of the five-port submultiplexer/demultiplexers; each of the 4.8Kbs office channel units is optionally connected to one of the ports ofthe five-port or 10-port submultiplexer/demultiplexers; and each of theoffice channel units of the 2.4 Kbs data customers is optionallyconnected to one of the ports of the five-port, 10-port or 20-portsubmultiplexer/demultiplexers; and, finally, the common two-way trunksof each of the submultiplexer/demultiplexers are connected to any portof multiplexer/demultiplexer 115. It is obvious that these optionsprovide great flexibility for a central office.

In FIG. 1, terminal 120 is shown strapped to terminal 135, connectingoffice channel unit 107 with port 1 of submultiplexer/demultiplexer 116via path 142. Terminal 121, of 4.8 Kbs subscriber's office channel unit109, may optionally be strapped to cross-office path terminal 126 or127. Terminal 127, in turn, is connected by way of two-way path 138 toport 1 of submultiplexer/demultiplexer 117. Terminal 126 isadvantageously connected by way of a two-way path, not shown, to afive-port submultiplexer/demultiplexer. As seen in FIG. 1, terminal 121is strapped to terminal 127 and 4.8 Kbs subscriber's office channel unit109 is, therefore, interconnected with a port ofsubmultiplexer/demultiplexer 117. It is to be understood that terminal121 may be optionally strapped to various other ones of the terminalsconnected to two-way paths extending to ports in submultiplexers 116 or117.

Similarly, terminal 122 of 4.8 Kbs subscriber's office channel unit 110may be strapped to terminals connected to ports in submultiplexers 116or 117. As seen in FIG. 1, terminal 122 is connected to two-way pathterminal 128 and this latter terminal is connected to a port ofsubmultiplexer/demultiplexer 116 by way of two-way path 137.

An inspection of the office channel units for the 2.4 Kbs subscribersdiscloses that these units may optionally be connected to a five-port, a10-port, or a 20-port submultiplexer/demultiplexer. In FIG. 1 it isshown that terminal 123 is strapped to terminal 132, connecting officechannel unit 111 to port 1 of submultiplexer/demultiplexer 118 by way oftwo-way path 139. Other arrangements are shown for office channel unitsconnected to 2.4 Kbs subscribers, wherein the office channel unit isconnected to five- and 10-port submultiplexer/demultiplexers. Forexample, office channel unit 112 is connected by way of terminals 124and 133 and cross-office path 140 to submultiplexer/demultiplexer 116.Similarly, office channel unit 113 is connected by way of terminals 125and 134 and cross-office path 141 to submultiplexer/demultiplexer 117.

In accordance with the specific embodiment disclosed herein, two-waytrunk 101 conveys multiplexed data having a signaling rate of 1.544megabits per second (Mbs). Digital data applied to the various ports ofmultiplexer/demultiplexer 115, together with certain synchronizing andframing data, is multiplexed in a manner described hereinafter bymultiplexer/demultiplexer 115 and then applied to two-way trunk 101.Conversely, incoming multiplexed data on two-way trunk 101 isdistributed to the various above-mentioned ports or utilized to obtainsynchronizing and framing information. The signaling format of themultiplexed data on trunk 101 can be characterized as byte organized.Advantageously, a byte consists of eight bits of data and, with respectto digital data, all bits of the byte are dedicated to one channel orsubscriber.

The multiplexed data on trunk 101 is preferably organized into trunkframes. Each frame consists of 24 bytes, of which 23 bytes are digitaldata, and one byte is for synchronization and network control. Inaddition, a framing bit is provided for each frame. Thus, a frameconsists of 24 eight-bit bytes plus a framing bit, or a total of 193bits per cycle.

Incoming multiplexed digital data on two-way trunk 101 (from a remoteoffice, for example) is distributed by multiplexer/demultiplexer 115 tothe 23 ports (ports 1 and 23 being identified on the left side ofmultiplexer/demultiplexer 115, as shown in FIG. 1), a byte at a time.More specifically, the first byte in each frame is passed to port 1, forexample, the second byte to port 2, et cetera, down through thetwenty-third byte to port 23. Appropriate buffering is provided in eachport whereby the bytes are passed onto 23 two-way paths, such as paths143 through 146, at a 64 Kbs signaling rate. The details of anarrangement for demultiplexing a byte (or character) at a time isdisclosed in U.S. Pat. No. 3,466,397, to P. Benowitz et al. on Sept. 9,1969.

As previously described, data from the various data customers isprocessed by the office channel units (and, as previously noted, thedata from certain groups of customers also multiplexed by thesubmultiplexer/demultiplexers) and then applied to the several ports ofmultiplexer/demultiplexer 115 by way of two-way paths 143 through 146.As described in detail hereinafter, the office channel unit processingis such that the data on all of the cross-office paths is organized intoeight-bit bytes at a signaling rate of 64 Kbs and the data thusorganized is applied to the several ports 1 through 23 ofmultiplexer/demultiplexer 115. Multiplexer/demultiplexer 115 multiplexesthe data applied to the several ports, a byte at a time, and applies themultiplexed data to trunk 101. More specifically, during each lineframe, a byte from a first port, such as port 1, followed by a byte froma second port and eventually to a byte from a twenty-third port, such asport 23, is applied to two-way trunk 101. During each trunk frame, a24th byte (designating network control and/or synchronizing information)may also be applied to two-way trunk 101. In addition, a framing bit isapplied to two-way trunk 101 to complete a trunk frame of 193 bits. Theconsequent outgoing signaling rate of two-way trunk 101 is, therefore,1.544 Mbs. The details of a multiplexer having the capability ofmultiplexing a byte (or character) at a time is disclosed in theabove-mentioned P. Benowitz et al patent.

It is, of course, realized that multiplexer/demultiplexer 115 can employvarious types of synchronizing and framing controls, thereby modifyingthe signaling rate on two-way trunk 101, the only requirement being thatthe signaling rate on trunk 101 must accommodate the ports connected tothe cross-office paths which, in this embodiment, we have assumed to be23, creating a signaling rate of at least equal to 23× 64 Kbs, or 1.472Mbs. Adding the network byte and the framing bit, the rate becomes 1.544Mbs.

One function of the interchange of the synchronizing and framinginformation is to synchronize office clocks. The office shown in FIG. 1might, of course, contain a master clock and, to synchronize the remoteoffice, synchronizing information would have to be sent to the remoteoffice. Conversely, the master clock may be at the remote office andincoming synchronizing information would be utilized to phase lock theoffice clock of FIG. 1 to the remote clock. In the specific embodimentdisclosed herein, the office clock advantageously provides an 8 kHzsignal and a related 64 kHz signal. It is recalled that the framing bitin the multiplexed signal appears once per trunk frame, and thereforehas an 8 kHz signaling rate. Accordingly, one might utilize the framingbit to phase lock a 64 kHz clock, which, with appropriate countdowncircuitry, also provides an 8 kHz clocking signal. As described infurther detail hereinafter, the 64 kHz office clock and the 8 kHz officeclock are utilized as the timing signals for the severalsubmultiplexer/demultiplexers. The office clocks, in addition, areemployed to phase lock the subscriber loop local clocks, as described infurther detail hereinafter. Appropriate timing waves for the 8 kHz clockand the 64 kHz clock are shown as timing waves A and B, respectively, inFIGS. 4A and 4B. It was previously noted that the cross-office signalingformat was organized into eight-bit bytes at a 64 Kbs signaling rate. Asdescribed in detail hereinafter, the 64 kHz office clock controls thebit signaling rate and the 8 kHz office clock aligns the bytes so thatthe byte intervals on all cross-office paths coincide in time. A timingwave representing the eight-bit byte organization is shown as wave C inFIGS. 4A and 4B. The alignment of the byte intervals is depicted belowwave C, five successive byte intervals being identified as intervals Y₁through Y₅.

Each of the office channel units processes the data so that incomingdata from the subscriber is organized into eight-bit bytes and convertedto a signaling rate of 64 Kbs and outgoing data is recovered from thebyte organized 64 Kbs data on the cross-office paths and converted tothe customer's signaling rate. Retiming of the incoming and outgoingdata is provided by one or more local clocks phase locked to the centraloffice reference clocks, as previously indicated. With respect to theincoming data, each office channel unit aligns the bytes, organizedtherein, with the office byte intervals. The bytes from the variousoffice channel units therefore coincide in time.

We have previously noted that one group of subscribers has thecapability of signaling at a 64 Kbs rate, a two-way loop of such asubscriber being designated by loop 102. Office channel unit 106,therefore, does not have to provide any conversion of the signaling rateto retime the subscriber's data and apply that data to cross-office path143. It is contemplated, however, that office channel unit 106 might beconnected to a 56 Kbs subscriber. In that event, each eight-bit byteassembled by office channel unit 106 includes seven data bits from thesubscriber and a flag bit inserted by the office channel unit fornetwork control. The eight-bit byte is then aligned in the common byteinterval and applied to two-way cross-office path 143. Conversely, dataon two-way cross-office path 143 directed to office channel unit 106 isrecovered by detecting the seven bits of data in the eight-bit byte,sending the seven bits on to the local subscriber. Although the detailsof office channel unit 106 are not disclosed herein, the manner ofretiming the data, assembling the data into eight-bit bytes, and thearrangement for inserting a flag bit in the byte is advantageously thesame arrangement provided by the office channel units of lower bit ratesubscribers, which arrangements are described in detail hereinafter.

A 9.6 Kbs office channel unit, such as office channel unit 107, providestwo principle steps in converting data having a 9.6 Kbs signaling rateto eight-bit byte organized data having a 64 Kbs signaling rate. Thefirst step is to organize eight-bit bytes. This involves assembling sixdata bits received from the customer and inserting a bit for framing anda flag bit for network control. The second step is to repeatedly applythe eight-bit byte to two-way path 142 at the cross-office signal rateof 64 Kbs. Office channel unit 107, being connected to a 9.6 Kbscustomer, applies the byte five times to two-way path 142, all of thefive bytes being aligned within the common office byte intervals. As aresult of inserting or stuffing two bits into the byte and thenrepeating the byte five times, the signaling format on the two-way pathis organized into eight-bit bytes at a 64 Kbs signaling rate.

Data on two-way cross-office path 142 is recovered by office channelunit 107 by selecting one out of five bytes and detecting the six databits in the recovered byte. The data bits are then transmitted to thesubscriber at the subscriber's rate.

A 4.8 Kbs office channel unit, such as office channel unit 109, convertsdata from a 4.8 Kbs subscriber to the common cross-office path signalformat by building each byte from six data bits from the subscriber, aframing bit and a network control flag bit. Each byte is then repeatedten times and applied to the two-way path which, in this case, is path138. Repetition of the byte ten times produces the eight-bit byteorganization at the 64 Kbs signaling rate. Office channel unit 109similarly employs the local clock to align each of the bytes with theoffice byte interval. Office channel unit 109 recovers the data ontwo-way path 138 by selecting one out of ten bytes on the cross-officepath, detecting the six data bits therein and transmitting to thesubscriber the six bits at the subscriber's signaling rate.

In a similar manner, a 2.4 Kbs office channel unit, such as officechannel unit 111, develops bytes by utilizing six bits of the data fromthe 2.4 Kbs subscriber and inserting a framing bit and a flag bit. Thedeveloped byte is then repeated 20 times and passed on to thecross-office path by office channel unit 111. The resultant cross-officesignal is thereby organized into eight-bit bytes at the 64 Kbs signalingrate. Conversely, cross-office data is reconverted to the 2.4 signalingrate by detecting one out of 20 bytes, recovering the six bitsdesignating the data, and transmitting these six bytes to the subscriberat the 2.4 Kbs signaling rate.

An important feature is that all cross-office signaling is organizedinto eight-bit bytes and the bytes on all of the paths are aligned intocommon byte intervals. This permits a cross-office path to be connectedinto any port of a submultiplexer/demultiplexer or into any port ofmultiplexer/demultiplexer 115.

It was previously pointed out that 9.6 Kbs office channel units, 4.8 Kbsoffice channel units and 2.4 Kbs office channel units may be connectedto one of the ports of submultiplexer/demultiplexer 116. As describedhereinafter, submultiplexer/demultiplexer 116 interleaves the bytesapplied to its five ports and applies the interleaved bytes to itscommon two-way trunk 144. Under the timing control of the office clock,submultiplexer/demultiplexer 116 selects a byte from one port, such asport 1, during the common office byte interval and then selects a bytefrom the next successive port during the next successive byte intervaland proceeds through the cycle to port 5 and then repeates the cycling,beginning with port 1. It is, therefore, apparent that for each pathconnected to a port, a byte will be selected every fifth byte intervalfor application to the common two-way trunk.

Each path from a 9.6 Kbs office channel unit has each byte appliedthereto repeated five times. Consequently, one and only one byte of eachset of repeated bytes is selected by submultiplexer/demultiplexer 116and interleaved with bytes applied to other ports. When a 4.8 Kbs officechannel unit, such as office channel unit 110, is connected to a port ofsubmultiplexer/demultiplexer 116, two bytes of each set are applied tocommon two-way trunk 144 since the original byte is repeated 10 times.Similarly, four bytes of each set from a 2.4 Kbs office channel unit,such as office channel unit 112, are applied to common trunk 144 sincethis original byte is repeated 20 times. The data thus applied to trunk144 comprises interleaved eight-bit bytes at a 64 Kbs signaling rate,the same signaling rate as the data on cross-office path 143.

Data from trunk 101, demultiplexed by multiplexer/demultiplexer 115 andapplied to two-way trunk 144, is again demultiplexed bysubmultiplexer/demultiplexer 116. As described in detail hereinafter,submultiplexer/demultiplexer 116, under the control of timing signalsfrom the office clock, selects successive eight-bit bytes in successivebyte intervals and applies them to successive ones of the five ports.Each port then repeats the eight-bit bytes applied thereto five timesand applies the bytes, aligned in the byte intervals, to the two-waypath, such as two-way path 142, 137 or 140. Each of the two-way pathsthus has applied to it an eight-bit byte organized signal at a 64 Kbsrate.

In general, the operation of submultiplexer/demultiplexer 117 is similarto submultiplexer/demultiplexer 116. Submultiplexer/demultiplexer 117,however, has ten ports and, therefore, needs 10 byte intervals in orderto cycle through the ports. Submultiplexer/demultiplexer 117 applies theinterleaved bytes from the ten ports to common trunk 145. It istherefore apparent that one byte of each set of repeated bytes from a4.8 Kbs office channel unit is applied to trunk 145, whereas two bytesof each set of repeated bytes from a 2.4 Kbs office channel unit isapplied to trunk 145, whereas two bytes of each set of repeated bytesfrom a 2.4 Kbs office channel unit is applied to trunk 145.Submultiplexer/demultiplexer 117 demultiplexes data applied thereto fromtrunk 145 in a manner similar to the manner thatsubmultiplexer/demultiplexer 116 demultiplexes the data, with theexception that it applies successive bytes to 10 ports and each portrepeats the byte 10 times for application to the two-way path. The dataon the two-way path is consequently arranged in the eight-bitorganization at a 64 Kbs signaling rate.

Submultiplexer/demultiplexer 118 is arranged in a manner similar tosubmultiplexer/demultiplexer 117. Submultiplexer/demultiplexer 118, ofcourse, has 20 ports and therefore requires twenty byte intervals tocycle the ports when multiplexing the data. Only 2.4 Kbs office channelunits are connected to the ports and one byte of each set of repeatedbytes from the subscriber is applied to trunk 146. When demultiplexingdata on trunk 146, submultiplexer/demultiplexer 118 applies successivebytes to the 20 ports and each port repeats each byte twenty times.Eight-bit byte organized data at a 64 Kbs signaling rate is thus appliedto the cross-office path, such as path 139.

In accordance with the above description, it is apparent that all of thesignaling on the two-way paths is organized into eight-bit bytes havinga common alignment and having the same signaling rate. This permits theoptional strappings to provide office flexibility, as previouslydescribed.

The details of a typical submultiplexer/demultiplexer are shown in FIG.2. The submultiplexer/demultiplexer shown therein is provided with fiveports, as indicated on the left side of FIG. 2, and a common trunk, asindicated on the right side. Common to the five ports is ring counter202. Ring counter 202 is driven by the 8 kHz office reference clocksignal, which signal is applied to its CLOCK input. As a result thereof,a bit is stepped through the ring counter, successively energizing itsfive output leads, identified by the numerals 1 through 5. The bit isthen fed back to the BIT input and the cycle is repeated. Associatedwith the common trunk is ring counter 201, which is also driven by the 8kHz office reference clock signal and also successively energizes itsfive output leads, identified by the numerals 1 through 5. We havepreviously noted that the central office is synchronized with the remoteoffice. Advantageously, the remote office includes a correspondingfive-port submultiplexer/demultiplexer. Corresponding channels areconnected to the ports of this remote submultiplexer/demultiplexer andthe corresponding ring counters are stepped in phase with ring counters201 and 202 of the submultiplexer/demultiplexer in the local office.

The submultiplexer/demultiplexer shown in FIG. 2 may be consideredtypical of any of the five-port submultiplexer/demultiplexers in theoffice. The structures of the 10-port and 20-portsubmultiplexer/demultiplexers are substantially identical to thefive-port submultiplexer/demultiplexer with the exception that theappropriate number of additional ports is included for the 10-port or20-port submultiplexer/demultiplexers and the corresponding ringcounters therein provide a count of ten or twenty.

In the following description of the five-portsubmultiplexer/demultiplexer shown in FIG. 2, it will be assumed that itcomprises submultiplexer/demultiplexer 116 shown in FIG. 1. The commontrunk is therefore identified as two-way cross-office trunk 144. Port 1is connected to two-way cross-office path 138 and port 5 is connected topath 140. Each of the cross-office paths is shown as two leads, with theleads carrying the data from the office channel units to the five portsof the submultiplexer/demultiplexer being identified as leads 206(1)through 206(5) and the leads carrying the data applied thereto by thefive ports of the submultiplexer/demultiplexer being identified as leads207(1) through 207(5). Two-way trunk 144 is shown as two paths, the leadcarrying the data from multiplexer/demultiplexer 115 being identified aslead 212 and the lead carrying the data to multiplexer/demultiplexer 115being identified as lead 211.

Data on paths 206(1) through 206(5) is multiplexed and passed to lead211 of trunk 144 by way of AND gates 208(1) through 208(5),respectively, and OR gate 210. AND gates 208(1) through 208(5) aresuccessively enabled by the five output leads of ring counter 201. Aspreviously described, ring counter 201 is driven by the 8 kHz officereference clock and as a consequence each of the five output leads isenergized for a byte interval. When the first output lead is energizedAND gate 208(1) is enabled and, for this byte interval, the byte appliedto lead 206(1) is passed therethrough and then through OR gate 210 tolead 211 of trunk 144. The next 8 kHz clock pulse advances counter 201to AND gate 208(2) and disables AND gate 208(1). As a consequence, thebyte on lead 206(2), aligned within this next byte interval, is passedthrough the enabled AND gate and OR gate 210 to lead 211. In this mannerincoming bytes to successive ones of the ports are applied, interleaved,to trunk 144. The data received on lead 212 is distributed to eight-bitregisters 204(1) through 204(5), each of the registers being associatedwith a corresponding one of the ports. The distribution of the data iscontrolled by ring counter 202. As described above, ring counter 202 isdriven by the 8 kHz office reference clock. Each of the five leads ofring counter 202 are, therefore, energized for a byte interval. When thefirst output lead of ring counter 202 is energized, AND gate 215(1) isenabled and AND gate 216(1) is concurrently disabled by way of inverter214(1). The byte on lead 212 is, therefore, passed through AND gate215(1) and OR gate 217(1) and inserted into eight-bit registers 204(1)by way of input terminal DATA. Eight-bit register 204(1) shifts the datatherethrough under control of shift pulses provided by the 64 kHz officereference clock applied to the input terminal CLOCK. During the byteinterval eight shift pulses are applied to register 204(1), filling theregister with the eight bits of the byte on lead 212.

At the termination of the byte interval, ring counter 202 is advanced,its first output lead is de-energized and its second output lead isenergized. Its second output lead provides the insertion of the byte onlead 212 into eight-bit register 204(2) in the same manner as theprevious byte was inserted in eight-bit register 204(1). Thede-energization of the first output lead 1 of ring counter 202 disablesAND gate 215(1) and enables AND gate 216(1).

During the second byte interval a second set of eight shift pulses isapplied to register 204(1). The eight-bit byte stored in the registerduring the first byte interval is shifted out onto lead 207(1) and thuspassed out through port 1 and path 138 to the office channel unit. Atthe same time, the eight bits of the byte are recirculated back throughAND gate 216(1) and OR gate 217(1) and reinserted back into register204(1). This process is then repeated for the third, fourth and fifthbyte intervals. Ring counter 202 is thus recycled to reenergize itsfirst output lead. The byte in register 204(1) is applied to lead 207(1)for the fifth time. AND gate 216(1) is now disabled to preclude therecirculation of the byte. AND gate 215(1) is enabled, however, so thatthe byte on trunk 144 is inserted in the register. Thus, port 1 selectsone of the five interleaved bytes on lead 212, repeats the byte fivetimes and passes it to lead 207(1). Each of the other ports operates insubstantially the same manner to accept another one of the interleavedbytes from lead 212, repeating the byte five times and passing it outthrough the output port.

The details of an office channel unit are shown in FIG. 3. This officechannel unit is specifically arranged to terminate a two-way loopextending to a 9.6 Kbs subscriber. As discussed hereinafter, the officechannel units terminating other signaling rate subscribers are arrangedin a similar manner to the 9.6 office channel unit.

As seen in FIG. 3, the 9.6 office channel unit is identified as officechannel unit 107, previously discussed relative to FIG. 1. The two-waycross-office path therefore extends to submultiplexer/demultiplexer 116,FIGS. 1 and 2, and comprises outgoing path 206(1) and incoming path207(1). The two-way loop extending to the subscriber comprises outgoingpath 301 and incoming path 302.

Incoming data derived from the submultiplexer/demultiplexer over path207(1) is clocked into six-bit (six-stage) register 308 and shiftedtherethrough by a "composite shift clock" applied to lead 305, thetiming wave thereof being identified as timing wave G, shown in FIGS. 4Aand 4B. The output of register 308 is clocked into flip-flop 309 by a"9.6 kHz data clock" applied to lead 304, the timing wave of this latterclock being identified as timing wave E in FIGS. 4A and 4B. The outputof the flip-flop 309 is then passed to lead 301 of the two-way loop.

Data from the subscriber received over lead 302 is clocked into andshifted through six-bit (six-stage) register 314 by the 9.6 kHz dataclock on lead 304. The data information in six-bit register 314 istransferred, in parallel, to eight-bit (eight-stage) recirculatingregister 315, the "transfer pulse" being provided to lead 307 and thetiming wave thereof being identified as timing wave H in FIGS. 4A and4B. The data in eight-bit recirculating register 315 is shifted by a 64kHz recirculating clock on lead 306, the timing wave thereof beingidentified as timing wave D in FIGS. 4A and 4B. The output data ofregister 315 is clocked into flip-flop 318 by the 64 kHz recirculatingclock pulses on lead 306 and, in addition, is recirculated back into theinitial or first stage of register 315. The output of flip-flop 318 isapplied to lead 206(1) of the two-way cross-office path.

The several clock waves described above are generated, in a mannerdescribed in detail hereinafter, by a local clock circuit, generallyshown as block 320. The 64 kHz recirculating clock (timing wave D)comprises a pulse train which is phase locked to the 64 kHz officereference clock. As seen in FIGS. 4A and 4B, each of the 64 kHzrecirculating clock pulses is coincident in time with a positivetransition of the 64 kHz office reference clock. The 9.6 kHz data clock(timing wave E) is generated by producing sets of six pulses. The firstpulse of each set is phase locked to an 8 kHz office reference clockpulse and the 9.6 kHz clock pulses are delayed so that the first twopulses of each set appear in the byte interval identified as byteinterval Y₁ in FIG. 4A.

For purposes of the following discussions, it is noted that theinterpulse interval between the first and second pulses of eachsix-pulse set of the 9.6 kHz data clock is identified as interval 1.Succeeding intervals are identified as intervals 2 through 5 and thesixth interval is identified as interval 0 (as seen in FIG. 4B). It isalso noted that the first bit of each of the cross-office bytes (wave C)is identified as bit 1 in FIG. 4A. Succeeding bits are identified asbits 2 through 8.

Each transfer pulse (wave H) occurs at the midpoint of those bit 8's ofthe bytes which appear on the two-way path during interval 0 of the 9.6kHz data clock. The composite shift clock (wave G) comprises a compositeof the 9.6 kHz data clock pulses and a six-pulse burst shown as wave Fin FIGS. 4A and 4B. As described in detail hereinafter, the six-pulseburst is derived from those negative transitions of the 64 kHz officereference clock which occur at the midpoints of bits 2 through 7 in thebyte of the 64 Kbs data appearing on the two-way path during the firstbyte interval, such as interval Y₁. Composite shift clock wave Gtherefore comprises an eight-pulse burst during the first byte interval(such as byte interval Y₁) and a sequence of four more pulses (from the9.6 kHz data clock) in the subsequent four byte intervals.

Assume now that data is being received from thesubmultiplexer/demultiplexer over lead 207(1). It was previouslydisclosed that the data destined for the subscriber constituted bits 2through 7 of the data byte. In addition, the byte is repeated five timesby the submultiplexer/demultiplexer. The useful data that is to beforwarded to the subscriber is therefore limited to bits 2 through 7 ofeach fifth byte, such as the byte in interval Y₁. All other data is tobe discarded and will hereinafter be referred to as "garbage."

Assume now that the first pulse of the eight-bit burst of the compositeshift clock appears on lead 305. The data on lead 207(1) is shifted intothe first stage of six-bit register 308, storing "garbage" in the firststage. The second pulse of the eight-pulse burst of the composite shiftclock gates bit 2 of the byte into the first stage of register 308 andconcurrently shifts the "garbage" into the second stage. Thereafter, thethird, fourth, fifth, sixth and seventh pulses of the eight-pulse burstgate in the third, fourth, fifth, sixth and seventh bits of the byteinto register 308, shifting the bits through the register at the sametime. This seventh pulse of the burst therefore fills register 308 withbits 2 through 7 of the byte, the "garbage" being discarded from thefinal stage.

The eighth pulse of the eight-pulse burst of the composite shift clockcoincides in time with (or immediately follows) the second pulse of the9.6 kHz data clock (which pulse initiates interpulse interval 2). The9.6 kHz data clock pulse is applied to the TOGGLE input of flip-flop309, while the output of the final stage of register 308 is applied,double rail, to the SET and CLEAR inputs of the flip-flop. Accordingly,bit 2 in the final stage of register 308 is toggled into flip-flop 309.The composite shift clock pulse concurrently shifts bit 3 of the byteinto the last stage while gating "garbage" from path 207(1) into thefirst stage of register 308.

During the 9.6 kHz clock interpulse interval 2, bit 2 of thecross-office byte is applied to lead 301 of the two-way loop byflip-flop 309. At the termination of this interval, bit 3 of thecross-office byte is toggled into flip-flop 309 by the 9.6 kHz clockpulse. The composite shift clock pulse moves up bits 4 through 7 of thecross-office bit, shifting byte 4 into the final stage of register 308and gating "garbage" into the first two stages. For each of thesucceeding fourth through sixth 9.6 kHz data clock pulses, the pulses,the fourth through sixth bits of the cross-office byte are similarlytoggled into flip-flop 309. The seventh bit of the cross-office byte isnow shifted into the final stage of six-bit register 308 and the firstfive stages are filled with "garbage."

The next pulse of the 9.6 kHz data clock, following interval 0,constitutes the first pulse of the new cycle. This toggles the seventhbit of the cross-office byte into flip-flop 309. The corresponding pulseof the composite shift clock now completely fills six-bit register 308with "garbage." (It is to be noted, however, that this first pulse ofthe composite shift clock may be blocked out as unnecessary to theproper operation of six-bit register 308). The composite shift clockpulses, starting with the pulse terminating interval 0, constitute theeight-pulse burst. As previously described, this burst reads intoregister 308 bits 2 through 7 of the byte, discarding the "garbage"preceding the bits. The new byte is thereafter read out to thesubscriber rate in the same manner as the readout of the previous byte.Accordingly, as described above, data bits 2 through 7 of each fifthcross-office byte are inserted in register 308 and read out to thesubscriber at the 9.6 kHz rate.

Data received from the 9.6 kHz customer over lead 302 is clocked intosix-bit register 314 by the 9.6 kHz data clock. It is apparent from aninspection of timing wave E in FIGS. 4A and 4B that six bits areinserted in register 314 during five cross-office byte intervals.

Near the termination of the fifth byte interval Y₅ a transfer pulse isprovided to lead 307. This gates the six bits of data in register 314into stages 2 through 7 of recirculating register 315. At the same time,a phase bit which is derived from a 0 bit on lead 317 is inserted intothe first stage and a flag bit is inserted into the last stage ofregister 315. The flag bit is provided by control bit generator 316,which generator operates to provide an appropriate network control bitin a manner not shown. More specifically, control bit generator 316 mayapply a constant 1 bit (positive potential) or a 0 bit (groundpotential) or, alternatively, may respond to external means toalternatively apply a 1 or 0 bit in accordance with the externalcontrol. In any event, the transfer pulse shifts eight bits into theeight stages of recirculating register 315, which eight bits willconstitute the repeated cross-office byte.

The 64 kHz recirculating clock on lead 306 sequentially shifts the eightbits to the double rail output of register 315, toggling the bits intoflip-flop 318. The output of register 315 is concurrently recirculatedback into the first stage of the register.

Eight pulses of the 64 kHz recirculating clock occur during each byteinterval. During the first byte interval Y₁, the eight bits in register315 are therefore toggled into flip-flop 318 and applied to path 206(1)of the two-way path. In this manner, the eight bits are organized into abyte and applied to path 206(1) during the byte interval Y₁ as shown intiming wave C in FIG. 4A.

At the termination of the byte interval the eight bits have been appliedto path 206(1) and have also been recirculated back through register315, with the 0 bit (phasing bit) back in the final stage. During thesecond byte interval (Y₂), the third byte interval (Y₃), the fourth byteinterval (Y₄) and the fifth byte interval (Y₅) the eight bits are againtoggled into flip-flop 318 to be applied to lead 206(1) and recirculatedback through the first stage in the same manner as the bits of the byteare passed to lead 206(1) and recirculated during byte interval Y₁. Atthe same time, the next six bits of data from the subscriber areinserted in register 314.

Near the termination of the byte interval Y₅ the transfer pulseoverwrites these next six bits into stages 2 through 6 of recirculatingregisters 315. The new byte is thus organized and repeatedly applied tothe two-way path during the succeeding five byte intervals.

A 64 Kbs customer's office channel unit need only retime the datapassing therethrough. In accordance therewith these office channel unitsneed only include flip-flops corresponding to flip-flops 309 and 318,together with the 64 kHz recirculating clock to toggle the data into theflip-flops. The 4.8 Kbs and 2.4 Kbs office channel units are arranged insubstantially the same manner as the 9.6 office channel unit, with theexception that the 9.6 kHz data clock is removed and a 4.8 or 2.4 kHzdata clock is substituted therefor and, in addition, one eight-pulseburst of the composite shift clock and one transfer pulse occur for each10 or 20 byte interval, respectively, instead of for each five byteinterval.

As previously mentioned, the clock signals produced by each local clock,such as clock 320, are phase locked with the 64 kHz and/or the 8 kHzoffice reference clocks. The 64 kHz office clock is received on lead353, which lead extends to phase-locked loop 321. Phase-locked loop 321comprises comparator 322, voltage-controlled oscillator 323 anddivide-by-3 downcounter 324. Voltage-controlled oscillator 323 includesa high frequency oscillator, together with downcounters which provide,at the output thereof, a 192 kHz square wave. This 192 kHz wave outputis applied to divide-by-3 downcounter 324 and to AND gate 328.

Divide-by-3 downcounter 324 produces at the output thereof a 64 kHzsquare wave. The wave is applied, in parallel, to one input ofcomparator 322, to monopulser 325, to inverter 326 and to AND gate 332.The other input of comparator 322 is lead 353 which carries the 64 kHzoffice reference clock. Comparator 322 therefore applies an errorvoltage to voltage-controlled oscillator 323 when the inputs thereof arenot phase locked to each other. This error voltage modifies the outputfrequency of voltage-controlled oscillator 323, modifying in turn theoutput frequency of downcounter 324 to reduce, in turn, the phase error.Phase-locked loop 321 therefore operates to provide at one outputthereof a 192 kHz wave and at a second output thereof a 64 kHz wave, thelatter wave being locked in phase with the 64 kHz office referenceclock.

The 64 kHz square wave derived from phase-locked loop 321 is utilized toderive the 64 kHz recirculating clock which is identified as wave D inFIGS. 4A and 4B. This is accomplished by monopulser 325, which providesan output pulse at each positive transition of the 64 kHz square wave.The output pulses of monopulser 325 are passed to lead 306, which leadconveys the 64 kHz recirculating clock pulses to the office channelunits, as previously described.

The 64 kHz square wave provided by phase-locked loop 321 also isutilized in the derivation of the six-pulse burst (wave F) and thetransfer pulse (wave H). The 64 kHz wave is applied to inverter 326 andthe inversion of the wave is passed to monopulser 327. The output ofmonopulser 327 comprises a pulse for each negative transition of the 64kHz square wave. This output is passed to gates 347 and 351, which, asdescribed hereinafter, are involved in the production of the six-pulseburst and the transfer pulse.

The 9.6 kHz data clock (wave E) is derived from the 192 kHz wave outputof phase-locked loop 321. As previously noted, this wave output ispassed to AND gate 328. Assuming that AND gate 328 is enabled, the 192kHz wave is passed therethrough to divide-by-20 downcounter 329. Theresultant output wave of downcounter 329 is therefore a 9.6 kHz squarewave. This square wave is passed through delay circuit 330 andmonopulser 331. The output of monopulser 331 comprises a pulse for eachpositive transition of the delayed 9.6 kHz square wave. The output ofmonopulser 331 is connected to gate 348 and to lead 304. This outputconstitutes the 9.6 kHz data clock passed to the office channel units.

As previously discussed, the 9.6 kHz data clock constitutes sets of sixpulses wherein the first pulse of each set is "phase locked" with theeight kHz office reference clock. The phase locking is accomplished bydowncounter 329 together with divide-by-6 counter 334, 0-count detector340 and AND gate 328 (downcounter 334 provides other functions,described later). 0-count detector 340 comprises AND gate circuitrywhich provides an energizing potential at its output when the severalstages of downcounters 329 and 334 indicate that the composite of thetwo downcounters is in the 0 count. Therefore, when downcounters 329 and334 are in the composite 0 count, inverter 343 removes the applicationof an enabling potential through OR gate 344 to AND gate 328. AND gate328 is therefore disabled until a pulse is applied to lead 354 by the 8kHz office clock. This pulse on lead 354 is passed through OR gate 344to enable AND gate 328. With AND gate 328 enabled, the 192 kHz squarewave is passed through downcounter 329, the count of the downcounter isadvanced (to 1), 0-count detector 340 removes the enabling potentialapplied to inverter 343 and the inverter, in turn, applies an enablingpotential through OR gate 344 to AND gate 328. Accordingly, to initiatethe count of downcounters 329 and 334 from their 0 count, it isnecessary that an 8 kHz office clock pulse appears on lead 354.

After advancing from the 0 count, downcounter 329 proceeds to count the192 kHz square wave, producing a cycle of the 9.6 kHz square wave andadvancing downcounter 334 for each twenty counts of the 192 kHz squarewave. After six of these cycles, the cumulative count returns to 0 andthe enabling of AND gate 328 can be provided only by the 8 kHz officeclock. In this manner, each sixth cycle of the 9.6 kHz square wave isphase locked to each fifth pulse of the 8 kHz office reference clock,aligning each first pulse in sets of six with each fifth pulse of thereference clock. The delay provided by delay circuit 330 is arranged tobe sufficient to align the first and second pulses in the set to framethe six-pulse burst (wave F).

The output count of downcounter 334 is also provided to 0-count detector341 and 1-count detector 342. In general, it is the function ofdivide-by-6 downcounter 334 to define the six interpulse intervals ofthe 9.6 kHz wave. 1-count detector 342 identifies the first interpulseinterval. Delay circuit 346 provides delay corresponding to delaycircuit 330. Delay circuit 346 thereby provides an enabling potential topartially enable AND gate 347 during the first interpulse interval ofthe 9.6 kHz data clock.

0-count detector 341 detects the 0 (or six) count of downcounter 334.During this interval an enabling potential is applied to delay circuit350 and delay circuit 350, in turn, provides an enabling potential topartially enable AND gate 351 during the 0 interpulse interval of the9.6 kHz data clock.

The various bit intervals of cross-office bytes are identified bydivide-by-8 downcounter 333. The input to downcounter 333 is provided bythe 64 kHz square wave output of phase-locked loop 321 which is passedthrough AND gate 332. The various counts of downcounter 333 are detectedby 1-count detector 337 and 3- through 0-count detectors, the first andlast thereof shown as blocks 335 and 336.

The output of 0-count detector 336 is applied through inverter 338 to ORgate 339. The other input to OR gate 339 extends to the 8 kHz officeclock by way of lead 354. The output of OR gate 339, in turn, isconnected to the enabling input of AND gate 332. AND gate 332 istherefore enabled by 0-count detector 336 via inverter 338 during sevencounts of downcounter 333. When the count of downcounter 333 is at 0,however, the enabling of AND gate 332 must be provided by the 8 kHzoffice clock. Downcounter 333 is therefore phase locked to the 8 kHzoffice clock.

Referring to FIGS. 4A and 4B, it can be seen that the 8 kHz clock pulseoccurs during bit 8 interval of the cross-office byte. Therefore,downcounter 333 is in the count of 1 during bit 8 interval, in the countof 2 during the bit 1 interval, and in the counts of 3 to 0 during thebit 2 to 7 intervals. The composite counts of 3 through 0 derived fromcount detectors 335 through 336 thereby define the bit 2 to 7 intervalsof the cross-office byte. Accordingly, during this six-bit interval oneof the count detectors 335 through 336 provides an energizing potentialthrough OR gate 356 to AND gate 347.

It was previously disclosed that AND gate 347 was partially enabled bydelay circuit 346 during the first interpulse interval of the 9.6 kHzdata clock. AND gate 347 is therefore enabled during the bit 2 to bit 7intervals which occur during the first interpulse interval of the 9.6kHz data clock, these being the bits in the first byte which is on thecross-office path during interval Y₁.

AND gate 347, enabled, passes the output of monopulser 327 to OR gate348. The output of monopulser 327 comprises pulses coinciding with eachnegative transition of the 64 kHz square wave output of phase-lockedloop 321, which pulses coincide with the theoretical midpoints of thebits. AND gate 347 therefore passes to OR gate 348 a six-pulse burst,the pulses occurring at the midpoints of bits 2 through 7 of the firstbyte. OR gate 348 combines the outputs of AND gate 347 and monopulser331, thus combining the 9.6 kHz data clock wave and the six-pulse burstto form the composite shift clock previously identified as wave G. Thiswave is passed to lead 305 and then to the office channel units.

The output of 1-count detector 337 is provided to AND gate 351, aspreviously noted. AND gate 351 is therefore partially enabled during thefirst count, which occurs during the eight bit of the cross-office byte.As previously described, AND gate 351 is also partially enabled by theoutput of delay circuit 350, which enablement occurs during interpulseinterval 0 of the 9.6 kHz data clock. AND gate 351 is therefore enabled,during that eighth bit of the byte which occurs during the 0 interpulseinterval of the 9.6 kHz clock, to pass therethrough the output ofmonopulser 327. The output of monpulser 327 constitutes pulsescoinciding with negative transitions of the 64 kHz square wave derivedfrom phase-locked loop 321 and AND gate 351 passes a pulse therethrough,when enabled. This comprises the transfer pulse (wave H) which isapplied via lead 307 to the office channel units.

Output leads 304 through 307 of local clock 320 are passed through cable303 to the various 9.6 Kbs office channel units, as previouslydescribed. Advantageously, the 64 kHz recirculating clock signals onoutput lead 306 are also passed to the 64 Kbs office channel units. The4.8 Kbs and 2.4 Kbs office channel units require 4.8 kHz and 2.4 kHzdata clocks, respectively, together with eight-pulse bursts of thecomposite shift clock and transfer pulses which occur every 10th and20th byte interval. Local clocks to provide these waves are individuallyarranged substantially in the same manner as clock 320, with theexception that the local clock for 4.8 Kbs office channel unitsadvantageously includes a divide-by-2 downcounter at the output of thedivide-by-20 downcounter corresponding to downcounter 329 in local clock320. The output of the divide-by-2 counter would then be delayed andpulses would be generated to coincide with each positive transition toprovide the 4.8 kHz data clock signal. The 0-count detectorcorresponding to detector 340 examines the cumulative count in thestages of the divide-by-20, divide-by-2 and divide-by-6 downcounters andthe 0- and 1-count detectors corresponding to detectors 341 and 342monitor the cumulative count in the stages of the divide-by-2 anddivide-by-6 downcounters. In a similar manner, a local clock for 2.4 Kbsoffice channel units is provided by substituting a divide-by-4downcounter for the divide-by-2 downcounter of the 4.8 Kbs officechannel unit local office clock.

Although a specific embodiment of this invention has been shown anddescribed, it will be understood that various modifications may be madewithout departing from the spirit of this invention.

What is claimed is:
 1. A multiplexing system comprising:a plurality of input terminals for providing data signals, means for repeating each of the data signals from each of the terminals a number of times, .Iadd.to achieve a high speed signaling rate, .Iaddend.the number being at least equal to the number of terminals, .[.to achieve a high speed signaling rate,.]. .Iadd.whereby successive groups of repeated data signals from each terminal are formed, each group consisting of the number of repeated data signals, .Iaddend.the repeating means including means for aligning in time each of the repeated data signals .Iadd.in each of the groups .Iaddend.with repeated data signals from the other terminals, and .Iadd.for serially applying the successive groups of repeated data signals from each terminal to an individual signal path associated with each of the terminals, and .Iaddend. means for interleaving one of .Iadd..[.each of.]. .Iaddend.the number of repeated data signals from .[.one of the terminals.]. .Iadd.each group of repeated data signals applied to each individual signal path .Iaddend.with .[.the.]. repeated data signals from the other terminals.
 2. A multiplexing system in accordance with claim 1 wherein each of the data signals provided by the terminals comprises a data byte, each of the data bytes comprises a plurality of serial data bits, and wherein the aligning .Iadd.and applying .Iaddend.means further includes means for aligning each of the serial bits in each of the bytes with corresponding bits in bytes from other terminals.
 3. A multiplexing system in accordance with claim 2 wherein each of the terminals includes means for receiving incoming data bits and means for assembling the incoming data bits into the data bytes.
 4. A multiplexing system in accordance with claim 3 wherein the assembling means further includes means for stuffing locally generated bits into each data byte whereby each byte consists of assembled incoming data bits and stuffed locally generated bits.
 5. A data signal multiplexing system comprising:a plurality of input terminals, each of the terminals conveying data signals at a signaling rate which differs from the signaling rate of other ones of the terminals, means associated with each of the terminals, for repeating each of the data signals from the terminal a number of times, the number being at least equal to and integrally related to the number of terminals and differing for each signaling rate in order to achieve a common high speed signaling rate, the repeating means including means for aligning in time each of the repeated data signals with repeated data signals from the other terminals, and means for sequentially scanning the repeated data signal outputs of the several repeating means at a scanning rate equal to the common high speed signaling rate.
 6. A multiplexing system in accordance with claim 5 wherein each of the data signals provided by the terminals comprises a data byte, each of the data bytes comprises a plurality of serial data bits, and the signaling rate defines the repetition rate of the repeated bytes, and wherein the aligning means further includes means for aligning each of the serial bits in each of the bytes with corresponding bits in bytes from other terminals.
 7. A multiplexing system in accordance with claim 6 wherein each of the terminals includes means for receiving incoming data bits and means for assembling the incoming data bits into the data bytes.
 8. A multiplexing system in accordance with claim 7 wherein the assembling means further includes means for stuffing locally generated bits into each data byte whereby each byte consists of assembled incoming data bits and stuffed locally generated bits.
 9. A data signal multiplexing system comprising:a plurality of input terminals providing data signals at one of at least two different signaling rates, one rate being a fixed multiple of the other rate, at least two groups of ports, the number of ports in one group being the fixed multiple of the number of ports in the other group, means associated with each one rate terminal for repeating the data signals a plurality of times .Iadd.to achieve a common high speed signaling rate, the plurality of times being .Iaddend.equal to the number of ports in the other group and means associated with each other rate terminal for repeating the data signals a plurality of times .Iadd.to achieve the common high speed signaling rate, the plurality of times being .Iaddend.equal to the number of ports in the one group, whereby a common high speed signaling rate is achieved, means for applying the output of each of the repeating means associated with one rate terminals to one of the ports in the other group, means for applying the output of at least one of the repeating means associated with another rate terminal to one of the ports in the other group and means for applying the outputs of other ones of the repeating means associated with other rate terminals to the ports in the one group, and means individual to each of the groups .[.of.]. .Iadd.for .Iaddend.sequentially scanning the ports in the group at a scanning rate equal to the common high speed signaling rate.
 10. A multiplexing system in accordance with claim 9 and further including means for aligning in time the data signal outputs of the repeating means associated with the one rate and the other rate terminals.
 11. A multiplexing system in accordance with claim 10 wherein each of the data signals provided by the terminals comprises a data byte, each of the data bytes comprises a plurality of serial data bits, and the signaling rate defines the byte repetition rate, and wherein the aligning means further includes means for aligning each of the serial bits in each of the bytes with corresponding bits in bytes from other terminals.
 12. A multiplexing system in accordance with claim 11 wherein each of the terminals includes means for receiving incoming data bits and means for assembling the incoming data bits into the data bytes.
 13. A multiplexing system in accordance with claim 12 wherein the assembling means further includes means for stuffing locally generated bits into each data byte whereby each byte consists of assembled incoming data bits and stuffed locally generated bits.
 14. A multiplexing system in accordance with claim 9 and further including means for multiplexing the signals scanned by the several sequential scanning means.
 15. A multiplexing system in accordance with claim 14 wherein there is included a further terminal providing data signals at the common high speed signal rate and wherein the multiplexing means includes means for multiplexing the signals provided by the further terminal with the signals scanned by the several sequential scanning means.
 16. A time-division multiplex system having a signaling format consisting of repetitive time frames, each time frame having n time slots, and including,a plurality of terminals providing .Iadd.serial .Iaddend.signals at a signaling rate which is the same as the time frame repetition rate, means associated with each of the terminals for repeating each .Iadd.serial .Iaddend.signal n times .[.and.]. .Iadd.whereby a group of n repeated signals is formed, .Iaddend.for aligning successive ones of the repeated signals with successive ones of the time slots, .Iadd.and for serially applying the successive groups of n repeated signals to an individual signal path associated with each of the terminals, .Iaddend.and means responsive to .Iadd.the successive group of n repeated signals on each individual signal path extending from .Iaddend.each of the terminal repeating and aligning means for inserting into .Iadd.any .Iaddend.one of the time slots in each of the .Iadd.successive .Iaddend.time frames the repeated data signal aligned therewith.
 17. A time-division multiplex system, in accordance with claim 16, and further including,other terminals providing signals at a signaling rate which is 1/m times the frame repetition rate, and means associated with each of the other terminals for repeating each signal m × n times and for aligning successive ones of the repeated signals with successive ones of the time slots.
 18. A time-division multiplex system, in accordance with claim 17, and further including,other means responsive to at least one of the other terminal repeating and aligning means for inserting into one of the time slots in each of the time frames the repeated data signal aligned therewith.
 19. A time-division multiplex system, in accordance with claim 17, and further having another signaling format consisting of other repetitive time frames, each having n × m time slots individually aligned with and having the same duration as the time slots of the n time slot time frames, and further including,means responsive to each of certain ones of the other terminal repeating and aligning means for inserting into one of the time slots in each of the other time frames the repeated data signal aligned therewith.
 20. A time-division multiplex system, in accordance with claim 19, and including,means for multiplexing the signals inserted into the time slots of the time frames with the signals inserted into the time slots of the other time frames. 